The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
State-of-the-art client and server processors may rely on on-die voltage regulators (VRs). On-die VRs may be elements of the processor that serve or regulate a voltage supplied to another element of the processor. In some processors, the on-die VRs may be referred to as fully integrated VRs (FIVRs). On-die VRs may be used to supply power to elements of the processor such as a memory controller, digital or analog input/output (I/O) ports or circuits, analog front end (AFE) ports or circuits, or other elements of the processor. In some cases, the on-die VRs may supply power to critical components such as delay-locked loop (DLL) and phase interpolator (PI) components which may directly impact the I/O system margin. In some cases, the I/O or AFE ports or circuits may be ports or circuits allowing communication with a double data rate (DDR) dynamic random access memory (DRAM) such as third generation (DDR3), fourth generation (DDR4), or some other type of DDR DRAM. In some cases, the I/O or AFE ports or circuits may be considered DDR ports or circuits. Similarly, in some cases the DRAM may be powered by an output voltage supplied by an external VR.